1. Field of the Invention
The invention relates to data transfers by system bus devices, and particularly to transfers by devices incapable of a bus master mode of operation.
2. Background Art
The IBM PC AT computer architecture has become industry standard architecture for personal computers, and is typically built around a CPU such as an 80286, 80386, 80486, or 80586 (Pentium.RTM.) microprocessor manufactured by Intel Corporation. The CPU is coupled to a host (local) bus, capable of performing memory accesses and data transfers at high rates of speed (i.e., on the order of 10-66 MHz). The host bus generally includes 16, 32, or 64 data lines, a plurality of address lines, and various control lines. For present purposes the following signals on the host bus are important:
______________________________________ Signal Name Signal Description ______________________________________ HD63:0! Host Bus Data Lines. HA31:3! Host Bus Address Lines. BE7:0!# Byte enables 7 through 0: Selects the active byte lanes on HD63:0!. INTR Interrupt Request: INTR is driven to signal the processor that an interrupt request is pending and needs to be serviced. M/IO# Memory/Input-Output: M/IO#, defines processor bus cycles along with D/C#, and W/R#. D/C# Data/Control: D/C# defines processor bus cycles along with M/I0# and W/R#. W/R# Write/Read: W/R# defines processor bus cycles along with M/I0# and D/C#. ADS# Address Strobe: The processor asserts ADS# to indicate that a new bus cycle is beginning BRDY# Burst Ready: BRDY# indicates that the system has responded in one of three ways: 1) Valid data has been placed on the processor data bus in a response to a read, 2) Processor write data has been accepted by the system, or 3) the system has responded to a special cycle. STPCLK# Stop Clock: this signal is connected to the STPCLK# input of the processor. It causes the processor to get into the STPGNT# state. ______________________________________
The typical IBM PC AT-compatible computer also includes a system bus, sometimes referred to as an I/O bus. Such a system bus is used to interface communications between a host CPU and a peripheral device, or communications between peripheral devices and host memory. The system bus is coupled to the host bus via certain interface circuitry. The system bus includes generally 8, 16, or 32 data lines, a plurality of address lines, as well as control lines.
One of the most commonly used system buses is the industry standard architecture (ISA) bus. The ISA bus was adopted by several computer industry groups in the 1980's to create a standard to permit the development of compatible add-on cards in a reasonable and consistent fashion. The ISA bus operates at approximately 8 Mhz and includes 8 or 16 data lines, distinct address lines, as well as distinct control and command lines.
The various signals on the ISA bus are well specified and known in the industry. General information on the ISA bus can be found in Solari, "AT Bus Design" (San Diego, Annabooks, 1990), incorporated by reference herein. For present purposes, the following ISA signals are important:
______________________________________ Signal Name Signal Description ______________________________________ SA23:0! 24 address lines. BALE Bus address latch enable line. BALE is an active high signal asserted to indicate when the SA address, AEN and SBHE# lines are valid. BALE remains asserted throughout ISA master and DMA cycles. SBHE# System byte high enable. When SBHE# is active, it indicates that a byte is being transferred on the upper byte (SD15:8!) of the data bus. AEN Address enable line. AEN is asserted during DMA cycles to prevent I/O slaves from misinterpreting DMA cycles as valid I/O cycles. When active, AEN informs I/O resources on the ISA bus that a DMA transfer is occurring. SD15:0! 16 data lines. MEMR# Read request lines to a memory resource on the ISA bus. MEMW# Write request lines to a memory resource on the ISA bus. IOR# Read request line to an I/O resource on the ISA bus. Also called IORC# or IORD#. IOW# Write request line to an I/O resource on the ISA bus. Also called IOWC# or IOWR#. M16# Memory chip select 16. Asserted by an addressed memory resource on the ISA bus if the resource can support a 16-bit memory access cycle. Also called MEMSC16#. I016# I/O chip select 16. Asserted by an addressed I/O resource on the ISA bus if the resource can support a 16-bit I/O access cycle. Also called IOCS16#. NOWS# Synchronous Ready line. Also sometimes called 0WS#, SRDY# or ENDXFR#. Activated by an addressed memory resource to indicate that it can support a shorter-than-normal access cycle. IOCHRDY I/O channel ready line. If this line is deactivated by an addressed I/O resource, the cycle will not end until it is reactivated. Also sometimes called CHRDY. INTRQ(15, Interrupt request lines. 14,12:9,7:3) DMARQ(7:5,3:0) DMA Request lines from I/O resource on ISA bus. DACK(7:5,3:0) DMA Acknowledge lines. BCLK ISA bus clock signal. XD7:0! XD bus lines. ISA status signals. ______________________________________
Recently, efforts have been made to develop other bus protocols for PC AT-compatible computers with the goals of reducing the size of PC AT-compatible computers as well as continued industry standardization. These efforts have included the development of the PCI bus, which has been developed to establish a new industry standard for bus architectures, particularly those interfacing with high bandwidth functions. The PCI bus is described in detail in "PCI Local Bus Specification", Revision 2.1 (Portland, Oreg., PCI Special Interest Group, 1995), incorporated by reference herein. For present purposes, the following PCI signals are important:
______________________________________ Signal Name Signal Description ______________________________________ AD31:0! PCI Address and Data: AD31:0! are bidirectional address and data lines for the PCI bus. FRAME# Cycle Frame: FRAME# is driven the current bus master to indicate the beginning and duration of an access. FRAME# is asserted to indicate that a bus transaction is beginning. While FRAME# is asserted, data transfers continue. When FRAME# is deasserted, the transaction is in the final data phase or has completed. IRDY# Initiator Ready: IRDY# indicates the initiating agent's (the bus master's) ability to complete the current data phase of the transaction. IRDY# is used in conjunction with TRDY#. A data phase is completed on each clock that both IRDY# and TRDY# are sampled asserted. During a write, IRDY# indicates that valid data is present on AD31:0!. During a read, it indicates the master is prepared to accept data. TRDY# Target Ready: TRDY# indicates the target agent's (selected device's) ability to complete the current data phase of the transaction. TRDY# is used in conjunction with IRDY#. A data phase is asserted. During a read, TRDY# indicates that valid data is present on Ad31:0!. during a write, it indicates the TRDY# is proper. DEVSEL# Device Select: When actively driven, DEVSEL# indicates the driving device has decoded its address as the target of the current access. STOP# Stop: STOP# indicates that the current target is requesting a master to stop the current transaction. PCICLK Master PCI clock. CLKRUN# Clock Run: CLKRUN# is an I/O sustained tristate signal used by the central resource (the host) to request permission to stop or slow the PCICLK. ______________________________________
Despite PCI bus development, because the PCI bus was designed primarily to support high-end peripherals (i.e., supporting speeds of up to 66 Mhz for 64-bit data), it is not as economical to manufacture low-end peripherals for the PCI-bus as it is for the older, slower ISA-bus. Thus both PCI-type devices and ISA-type devices are commonly produced and computer systems must be developed which have the interfaces to support both PCI-type and ISA-type devices.
Specific devices coupled to the system bus are often peripheral storage units such as disk drives and CD-ROM drives. Many of these devices are IDE (integrated device electronics) devices meaning that they have a built-in controller which allows them to directly interface with the system bus, often an ISA bus. To allow compatibility with various IDE devices and to develop industry standardization and systems, the AT Attachment-3 Interface Specification (ATA-3) has been developed by various industry groups. ATA-3 is described in detail in "Information Technology--AT Attachment-3 Interface (ATA-3), Revision 5 (released for comment and review by ASC X3T10 Technical Committee, October 1995), incorporated by reference herein. For present purposes, the following IDE signals (as defined by ATA-3) are important:
______________________________________ Signal Name Description ______________________________________ DA2:0! IDE address lines: asserted by host to access device. DD15:0! IDE data: bidirectional data lines DRD# Read request line to IDE resource DWR# Write request line to IDE resource. INTRQ Interrupt request. Asserted by IDE device when data is ready for transfer. DMARQ DMA request. Asserted by IDE device when IDE device is ready for a DMA transfer. DMACK# DMA acknowledge. DCS1#, DCS3# Chip select signals for selecting control block registers in IDE device. DCHRDY Channel ready: negated during an access cycle when device is not ready to respond to a data transfer request. ______________________________________
Generally, when a host system (which may include a processor, a memory, and interface circuitry) requires data from an IDE drive, the host will first write command parameters (e.g., sector count, sector number, head, etc.) and other command codes to device registers notifying the device of a request for data. When data is available for transfer to or from the device, the device asserts an interrupt (INTRQ) to the host system. Upon receipt of an interrupt, the host processor initiates an access cycle to transfer data to or from the device. Such mode of data transfer is often referred to as a "programmed I/O" (or "PIO") data transfer because of use made of programmable registers. Other methods of I/O transfer without using programmable registers are also known in the art. Thus, as referred to hereinafter, a "PIO" mode of data transfer is any I/O cycle requiring host processor resources throughout the access cycle. Generally the host processor remains actively involved in the PIO access cycle until it is completed, e.g., by waiting to receive data and then transferring the data to memory. More detailed information regarding PIO data transfers can be found in ATA-3.
Because of the high demand for host processor resources during an access cycle, many IDE drives are also "bus masters", meaning that the device itself can initiate and control a data transfer cycle on the system bus with little to no host processor participation. Often such "bus master" control occurs through DMA (direct memory access) cycles, which allow a device to transfer data to or read data from the host memory directly without host processor involvement.
Generally for a DMA transfer, when a host system requires data from a bus mastering IDE device, the host will first write command parameters and other command codes to IDE device registers, thereby notifying the device of a request for a data transfer, in a manner similar to that done for IDE devices using a PIO mode of transfer. However, rather than asserting an interrupt to the host processor, the bus-mastering IDE device will assert a DMA request signal (DMARQ), which is not transferred to the host processor. Rather the DMARQ signal is received by the interface circuitry and indicates that the IDE device is attempting to assert ownership of the bus. Upon receipt of a DMA acknowledge (DMACK) signal from the interface circuitry, indicating that the bus is available for ownership by the device, the IDE device transfers data to host memory via a DMA data transfer cycle. No host processor resources are utilized during a DMA data transfer. More detailed information regarding DMA data transfers to and from IDE devices can be found in ATA-3.
Some devices, however, particularly CD-ROM drives, do not have bus-mastering capability. These devices have no option but to transfer data to and from the host via a PIO data transfer, consuming valuable host processor resources. Unfortunately, CD-ROM devices use more host processor bandwidth in a data transfer than any other type of system I/O device currently available. Thus a data transfer involving a CD-ROM drive will consume considerable CPU resources, causing slower system performance.
As applications on CD-ROM and other high-bandwidth devices increase, such performance compromises are becoming more and more unacceptable. While some CD-ROM drives are beginning to be designed with bus mastering capability, the vast majority lack this ability. Thus, a device for improving the performance of computer systems during a data transfer involving a non-bus-mastering device is needed.